As CMOS manufacturing technology achieves smaller feature sizes, for example, 01. microns and below, there has been a corresponding scaling down of the gate dielectric. The scaled-down gate dielectric has become so thin that boron, which is traditionally used to dope the gate electrode for P-channel MOS field effect transistors, can migrate from the gate electrode through the thin gate dielectric and penetrate into the underlying semiconductor substrate, causing unwanted changes in the properties of the substrate.
Boron penetration may be reduced by incorporating nitrogen in the gate dielectric or polysilicon gate. However, that reduction is not usually sufficient for very thin gate oxides, and in addition it may even exacerbate the poly depletion effect.
The use of metal gate electrodes or fully silicided gate electrodes may reduce both the boron penetration and the poly depletion effect. However, these approaches have substantial drawbacks in that determining the right work function for such gate electrodes that is suitable for either of N or P channel devices (necessary for CMOS devices) is difficult. In addition, the interface of these materials with common gate dielectric materials, such as SiO2, is not nearly so well understood as the silicon (including polysilicon) and gate oxide interface, so the stability of these materials on a gate dielectric is an issue.
Accordingly, it is desirable to find a way to improve semiconductor device performance by reducing boron penetration while improving the poly depletion effect by achieving a better dopant activation in gate electrode, or at least without any deterioration of poly depletion effect in scaled down MOSFET devices.